Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device including a pipe latch circuit for storing output data during a read operation.
In general, semiconductor memory devices such as Double Data Rate Synchronous DRAM (DDR SDRAM) include a pipe latch circuit configured to receive parallel data stored in a memory bank during a read operation and serially output the received data.
FIG. 1 is a block diagram illustrating a conventional pipe latch circuit.
Referring to FIG. 1, the pipe latch circuit includes first to eighth pipe latching units 110 to 180 configured to sequentially latch parallel data inputted through first to eighth global data lines GIO<1:8> in response to first to eighth pipe input control signals PIN<1:8>, and sequentially output the latched data in response to first to eighth pipe output control signals POUT<1:8>. The number of pipe latching units is often determined by values of a CAS latency (CL), a burst length (BL), and a CAS to CAS delay (tCCD). For example, when the CL, the BL, and, the tCCD have values of 16, 4, and, 4 clocks (tCK), respectively, the number of pipe latching units may be set to five according to Equation 1 expressed below. In Equation 1, N represents the number of pipe latching units.N=(CL+BL)/tCCD  (1)
Referring to Equation 1, as the CL gradually increases, the number of pipe latching units gradually increases. As the operation frequency of semiconductor memory devices has gradually increased, the CL also has gradually increased. Accordingly, the number of pipe latching units is on the rise. The increase in the number of pipe latching units results in the increase in the circuit size.
FIGS. 2 and 3 are timing diagrams illustrating a circuit operation of a semiconductor memory device related to the pipe latch circuit of FIG. 1. FIGS. 2 and 3 show a case in which the number of pipe latching units is designed according to Equation 1. For convenience of explanation, the following description is focused on the latching operation of the first pipe latching unit 110.
Referring to FIGS. 1 and 2, read commands RD are consecutively applied during a period of n×tCCD. Here, the tCCD represents a time between a read command RD and a next command RD. Meanwhile, the semiconductor memory device internally generates a column selection signal in response to the read command RD, and first data DAT1 stored in the memory bank is transferred to the first to eighth global data lines GIO<1:8> in response to the column selection signal. Subsequently, the first pipe input control signal PIN<1> is activated when a period of tPIN passes after the read command RD is applied, and the first pipe latching unit 110 latches the first data DAT1 transferred through the first to eighth global data lines GIO<1:8> in response to the first pipe input control signal PIN<1>. The latched first data DAT1 is outputted from the first pipe latching unit 110 in response to a first pipe output control signal POUT<1> which is activated during a period of tPOUT. The outputted data is outputted through a data pad DQ. For reference, a case in which the data pad DQ outputs four data D1 corresponding to the first data D1 is taken as an example, which means that the BL is four.
The above-described series of operations may be applied to the second to eighth pipe latching units 120 to 180. That is, the first to eighth pipe latching units 110 to 180 sequentially latch parallel data which are consecutively inputted. Accordingly, after the data is latched in the eighth pipe latching unit 180 serving as the last pipe latching unit, data is latched in the first pipe latching unit 110. FIG. 2 shows such an operation. Second data DAT2 transferred through the first to eighth global data lines GIO<1:8> is latched in the first pipe latching unit 110.
The pipe latch circuit of the semiconductor memory device may perform an abnormal operation by such factors as a process, a voltage, and a temperature, which is illustrated with reference to FIG. 3.
Referring to FIG. 3, the first pipe input control signal PIN<1> is a signal which is activated during the read operation, and the activation time may be changed depending on the process, voltage, and temperature. Comparing FIG. 2 with FIG. 3, it can be seen that the period of tPIN of FIG. 3 becomes shorter than the period of tPIN of FIG. 2.
In this case, the first pipe latching unit 110 latches the second data DAT2, which is inputted after the latched first data DAT1, during a portion of the period in which the first pipe output control signal POUT<1> is activated. As a result, the data pad PQ outputs data D2 corresponding to the second data DAT2. As seen in FIG. 3, when the semiconductor memory device abnormally operates, the data pad DQ may output two data D1 corresponding to the first data DAT1, and subsequently outputs two data D2 corresponding to the second data DAT2.
Meanwhile, such an abnormal operation of the semiconductor memory device may be prevented by increasing the number of pipe latching units. However, when the number of pipe latching units increases, the area of the semiconductor memory device also increases, which may act as a burden in circuit design. Furthermore, the pipe latch circuit is to be provided in each data pad DQ. Considering a recent trend in which the number of data pads gradually increases, the increase in the number of pipe latching units may increase the burden in circuit design.